Integration and Evaluation of Different FPGA based Hard-ware Accelerators for the AES Algorithm in the TLS Protocol to be Used in Critical Automation Systems

This thesis addresses the challenges of hardware-assisted cryptography in the context of automation systems in critical infrastructures. While hardware accelerators enhance cryptographic calculations in both performance and security, their permanence poses issues in adapting to evolving security concerns. To overcome this problem, we inte-grated and evaluated a hardware accelerator for the AES algorithm on an FPGA within a TLS application, comparing its performance with other accelerators. Employing a hybrid FPGA-CPU processor system, this setup achieves over 800 Mbit/s data rates, showcasing a more than 27 times acceleration in TLS transmissions compared to purely software-based solutions. The FPGA's flexibility and upgradability therefore make it an ideal platform for critical infrastructure, ensuring longevity and superior ac-celeration in TLS data transfers.