Development and Integration of CCSDS 123.0-B-2 FPGA Accelerator for HYPSO-1

The HYPerspectral imaging small Satellite for Ocean observation (HYPSO) mission uses hyperspectralimages to monitor the environment by collecting images of up to hundreds of bands in the electromagneticspectrum. This mission relies on the use of reconfigurable hardware for acceleration of onboard compressionof hyperspectral images. This combats a challenge associated with small satellites as their constrained receiveand transfer bandwidths and storage capabilities paired with hyperspectral images introduce limitations intheir efficiency. Onboard compression is key in maximising satellite operational capacity by minimisingtime spent communicating and increasing the number of images that can be stored. The HYPSO-1 satellitecurrently uses a hyperspectral image compressor; CCSDS 123.0-B-1 standard on a Field-Programmable GateArray (FPGA) accelerator to compress its hyperspectral images. With the development of a near-losslessCCSDS 123.0-B-2 compliant encoder accelerator, this work has provided state-of-the-art compression speedsfor implementations on smaller off-the-shelf FPGAs such as the ZYNQ-7000 series. This work describes theB-2 accelerator, the testing procedure in which upon successful RTL simulations the accelerator was testedon an on-ground HYPSO-1 system model and then passed integration tests in orbit on HYPSO-1, replacingB-1 as the defacto onboard standard in use.