DEPLOYING FIELD PROGRAMMABLE GATE ARRAYS FOR IMPROVING EFFICIENCY AND QUALITY IN 3D PROSTHETIC PRINTING

This work intends to address the challenges in improving the quality of additive manufacturing, or 3D printing, by optimizing print orientation algorithms deployed onto a field programmable gate array (FPGA). The core focus of this work studies the development of a high-speed brute-force scoring system by refining existing print orientation algorithms’ techniques. Successful implementation can reduce pre-processing print time, decrease print time, reduce print structural weakness, and increase print precision. While the core focus of this study is on refining and deploying a scoring system onto a FPGA, this research also explores its deployment using Vitis High Level Synthesis while exploiting the FPGA’s parallel processing. Finally, this study investigates the integration of the FPGA accelerator, specifically the Xilinx ZUboard 1CG, with the host machine using the ZUboard’s Dual-core Arm Cortex-A53 processor, Zynq UltraScale+, and Ethernet communication via the Lightweight IP (LWIP) stack. This approach provides a comprehensive framework for improving additive manufacturing’s efficiency, quality, and performance.