Design of 4-bit Binary Weighted DAC in 180nm CMOS Technology

In this paper, a method for implementing 4-bit binary weighted digital to analog converter using cadence virtuoso 180nm technology is presented. The presented DAC is designed at 1.8v power supply. Primarily a differential amplifier of gain 32.86db is followed by an operational amplifier of gain 56.90 db is designed using CMOS technology. A High gain operational amplifier helps in achieving better linearity and reduced distortions. The designing of this DAC involves creating transistor level schematic design followed by simulation using transient analysis. DAC’s serve as fundamental building blocks in various applications like Audio and communication Systems.

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2024-08-20
DOI
https://doi.org/10.5281/zenodo.13709785
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.00
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article

Design of 4-bit Binary Weighted DAC in 180nm CMOS Technology

Zenodo (CERN European Organization for Nuclear Research)
Analog and Mixed-Signal Circuit Design
article

Design of 4-bit Binary Weighted DAC in 180nm CMOS Technology

article en

Abstract

In this paper, a method for implementing 4-bit binary weighted digital to analog converter using cadence virtuoso 180nm technology is presented. The presented DAC is designed at 1.8v power supply. Primarily a differential amplifier of gain 32.86db is followed by an operational amplifier of gain 56.90 db is designed using CMOS technology. A High gain operational amplifier helps in achieving better linearity and reduced distortions. The designing of this DAC involves creating transistor level schematic design followed by simulation using transient analysis. DAC’s serve as fundamental building blocks in various applications like Audio and communication Systems.

Zenodo (CERN European Organization for Nuclear Research)
Affordable and clean energy
Openalex Percentile: Top 66%
Analog and Mixed-Signal Circuit Design
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Design of 4-bit Binary Weighted DAC in 180nm CMOS Technology · Zenodo (CERN European Organization for Nuclear Research) (2024) | TGRS Research Map | TGRS