Parallel Implementation of Direct Simulation Monte Carlo Using Field Programmable Gate Arrays

Abstract: Direct simulation Monte Carlo (DSMC) is a powerful but computationally demanding method for simulating rarefied gas flows. While most of its algorithm elements such as random number generation, advection, and sampling are embarrassingly parallelisable, collision evaluation poses challenges for effective parallelisation. Field-programmable gate arrays (FPGAs), are well suited to embarrassingly parallel problems and have been demonstrated to provide better performance and power efficiency than central processing units (CPU) and graphical processing units (GPU) for such problems. This paper presents a novel approach to implementing the DSMC method on FPGAs taking advantages of their architecture while also addressing these challenges. We introduce a variable bit-width custom random number generator (RNG) tailored for FPGA-based DSMC computations, demonstrating linear resource scaling and achieving a peak throughput of 13 Gbps for a 31-bit implementation. We provide as an example a calculation of Rayleigh flow and establish that an 11-bit RNG provides an optimal balance between accuracy and resource efficiency. The FPGA-based collision kernel using this custom RNG shows significant performance improvements over traditional implementations, outperforming a 64-bit XOR-shift by 1.36 times and a 64-bit Mersenne twister algorithm by more than 30 times, while consuming fewer FPGA resources than either algorithm. This efficiency enables the instantiation of six parallel collision kernels on the Pynq-Z2 FPGA, with the potential of around twenty times as many collision kernels on a larger FPGA like the Versal VPK120. Our approach overcomes key obstacles in parallel DSMC implementation on FPGAs, including efficient resource usage and prevention of race conditions in collision pair selection, paving the way for accelerated micro-scale flow simulations. Keywords: direct simulation Monte Carlo (DSMC), field-programmable gate array (FPGA), random number generation, collision evaluation, spatial parallelism, micro-scale flows