VLSI Methodology for Implementation of Iris Recognition Based on Singular Value Decomposition for Feature Extraction

In an Iris recognition System Feature extraction plays a very important role were the only useful dominant information from an eye images are extracted. The SVD algorithm is most focused in this paper were the SVD implemented in both Matlab and FPGA along with the Comparison results. The singular value decomposition is dimensionality reduction algorithm were Jacobi transform is used for parallel and fast computation; paper also focuses on the area and timing analysis. Jacobi algorithm for SVD calculation is used as it contains a large degree of parallelism. Architecture of SVD core which is implemented consists of 6 sub blocks and all are designed in FPGA were the 77% of overall area is utilized by 40x40 iris template image on target device in 211μsec time.

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2025-05-01
DOI
https://doi.org/10.5281/zenodo.15315803
Primary Topic
Biometric Identification and Security
Type
article
Field-Weighted Citation Impact
0.00
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article

VLSI Methodology for Implementation of Iris Recognition Based on Singular Value Decomposition for Feature Extraction

Zenodo (CERN European Organization for Nuclear Research)
Biometric Identification and Security
article

VLSI Methodology for Implementation of Iris Recognition Based on Singular Value Decomposition for Feature Extraction

article en

Abstract

In an Iris recognition System Feature extraction plays a very important role were the only useful dominant information from an eye images are extracted. The SVD algorithm is most focused in this paper were the SVD implemented in both Matlab and FPGA along with the Comparison results. The singular value decomposition is dimensionality reduction algorithm were Jacobi transform is used for parallel and fast computation; paper also focuses on the area and timing analysis. Jacobi algorithm for SVD calculation is used as it contains a large degree of parallelism. Architecture of SVD core which is implemented consists of 6 sub blocks and all are designed in FPGA were the 77% of overall area is utilized by 40x40 iris template image on target device in 211μsec time.

Zenodo (CERN European Organization for Nuclear Research)
Openalex Percentile: Top 47%
Biometric Identification and Security
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