A K-band gm-boost dual path noise-canceling LNA

To meet the demand for high-performance silicon-based low noise amplifier (LNA) with the development of communication systems, a gm-boost dual path noise-canceling circuit topology is proposed, which can reduce transistor noise and achieve low noise figure (NF). A gm-boost structure is introduced in the common-gate path to further improve the gain and noise performance. A K-band LNA is designed based on the topology mentioned above, consisting of two paths: a common-gate path and a common-source path, each of which acts as feedback branch of the other. Two paths are synthesized to achieve noise cancellation. The LNA is designed under a 90 nm CMOS SOI process, with a chip core size of 500 μm×280 μm. The simulation results show that a NF of 1.61~1.87 dB and a peak gain of 15.8 dB are achieved in 17~22 GHz. The input power with 1 dB gain compression is -4.3 dBm, demonstrating good noise and linear gain performance.

Publication Details

Journal
SHILAP Revista de lepidopterología
Published
2025-04-01
DOI
https://doi.org/10.16157/j.issn.0258-7998.256372
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
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article

A K-band gm-boost dual path noise-canceling LNA

SHILAP Revista de lepidopterología
Radio Frequency Integrated Circuit Design
article

A K-band gm-boost dual path noise-canceling LNA

article en

Abstract

To meet the demand for high-performance silicon-based low noise amplifier (LNA) with the development of communication systems, a gm-boost dual path noise-canceling circuit topology is proposed, which can reduce transistor noise and achieve low noise figure (NF). A gm-boost structure is introduced in the common-gate path to further improve the gain and noise performance. A K-band LNA is designed based on the topology mentioned above, consisting of two paths: a common-gate path and a common-source path, each of which acts as feedback branch of the other. Two paths are synthesized to achieve noise cancellation. The LNA is designed under a 90 nm CMOS SOI process, with a chip core size of 500 μm×280 μm. The simulation results show that a NF of 1.61~1.87 dB and a peak gain of 15.8 dB are achieved in 17~22 GHz. The input power with 1 dB gain compression is -4.3 dBm, demonstrating good noise and linear gain performance.

SHILAP Revista de lepidopterología
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Radio Frequency Integrated Circuit Design
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