Liquid Metal Oxide-Assisted\nIntegration of High‑k\nDielectrics and Metal Contacts for Two-Dimensional Electronics

Two-dimensional van der Waals semiconductors are promising\nfor\nfuture nanoelectronics. However, integrating high-k gate dielectrics\nfor device applications is challenging as the inert van der Waals\nmaterial surfaces hinder uniform dielectric growth. Here, we report\na liquid metal oxide-assisted approach to integrate ultrathin, high-k\nHfO<sub>2</sub> dielectric on 2D semiconductors with atomically smooth\ninterfaces. Using this approach, we fabricated 2D WS<sub>2</sub> top-gated\ntransistors with subthreshold swings down to 74.5 mV/dec, gate leakage\ncurrent density below 10<sup>–6</sup> A/cm<sup>2</sup>, and\nnegligible hysteresis. We further demonstrate a one-step van der Waals\nintegration of contacts and dielectrics on graphene. This can offer\na scalable approach toward integrating entire prefabricated device\nstack arrays with 2D materials. Our work provides a scalable solution\nto address the crucial dielectric engineering challenge for 2D semiconductor-based\nelectronics.

Publication Details

Journal
Figshare
Published
2024-09-18
DOI
https://doi.org/10.1021/acsnano.4c08554.s001
Primary Topic
Mycorrhizal Fungi and Plant Interactions
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article
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article

Liquid Metal Oxide-Assisted\nIntegration of High‑k\nDielectrics and Metal Contacts for Two-Dimensional Electronics

Figshare
Mycorrhizal Fungi and Plant Interactions
article

Liquid Metal Oxide-Assisted\nIntegration of High‑k\nDielectrics and Metal Contacts for Two-Dimensional Electronics

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Abstract

Two-dimensional van der Waals semiconductors are promising\nfor\nfuture nanoelectronics. However, integrating high-k gate dielectrics\nfor device applications is challenging as the inert van der Waals\nmaterial surfaces hinder uniform dielectric growth. Here, we report\na liquid metal oxide-assisted approach to integrate ultrathin, high-k\nHfO<sub>2</sub> dielectric on 2D semiconductors with atomically smooth\ninterfaces. Using this approach, we fabricated 2D WS<sub>2</sub> top-gated\ntransistors with subthreshold swings down to 74.5 mV/dec, gate leakage\ncurrent density below 10<sup>–6</sup> A/cm<sup>2</sup>, and\nnegligible hysteresis. We further demonstrate a one-step van der Waals\nintegration of contacts and dielectrics on graphene. This can offer\na scalable approach toward integrating entire prefabricated device\nstack arrays with 2D materials. Our work provides a scalable solution\nto address the crucial dielectric engineering challenge for 2D semiconductor-based\nelectronics.

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