Design and Implementation of Hybrid Full Adder-Based Ripple Carry Adder for Low Power Applications

Full adders are fundamental components in various applications, including Digital Signal Processors (DSPs) and microprocessors. In modern circuit design, reducing supply voltage has become a key approach to minimizing energy consumption. Since the full adder serves as a primary arithmetic unit in many computational tasks, it plays a crucial role in the efficiency of the Arithmetic Logic Unit (ALU). This project introduces novel hybrid full adder designs aimed at achieving low Power-Delay Product (PDP). Additionally, a Ripple Carry Adder (RCA) is proposed using a chain structure to enhance driving strength. The hybrid full adder topologies are implemented to construct a 4-bit RCA based on CMOS technology, optimizing power and performance.