Efficient Low-Power VLSI Design of a High-Speed Baugh-Wooley Multiplier Using Verilog HDL

The growing demand for portable systems and the necessity to reduce power consumption in ultra-high-density ULSI chips have driven rapid advancements in low-power design. Low-power optimization has become a critical concern in high-performance digital systems, including microprocessors, digital signal processing (DSP), and various computing applications. As portable computing and communication needs expand, power-efficient multipliers play a pivotal role in Very Large Scale Integration (VLSI) system design. Multiplication is a fundamental operation in numerous DSP algorithms, necessitating the development of efficient multiplier architectures. This project focuses on the implementation of a high-speed, low-power multiplier using the shift-and-add method of the Baugh-Wooley multiplier. The study explores the design and implementation of Baugh-Wooley multipliers, emphasizing a Modified Baugh-Wooley architecture that achieves minimal area, power, and delay. The design is developed using Verilog HDL and simulated and synthesized using the Xilinx ISE tool.