Integration of a CGRA Accelerator with a CVA6 RISC-V Core for the Cloud-edge Continuum

The computing continuum is a new paradigm that views the cloud, edge, and fog layers of the Internet of Things as part of a single space where computing tasks can be scheduled on various devices [1]. In this context, edge devices could benefit from application-class processors and reconfigurable accelerators to provide further adaptability and local processing capabilities. This master’s thesis has been elaborated at the Center for Industrial Electronics (CEI) of the Universidad Politécnica de Madrid (UPM). It targets the development of adaptable edge nodes for the cloud-edge continuum, applying technologies related to Coarse-Grain Reconfigurable Arrays (CGRAs) and RISC-V processors. This work has been carried out in the context of the MYRTUS project [2], funded by the European Union with grant number 101135183. More specifically, this master’s thesis aims to integrate a CGRA accelerator previously developed at CEI [3] with an application-class RISC-V processor on a System on Chip (SoC) and evaluate its performance when accelerating a set of tasks. The resulting system will then serve as a starting point for developing an edge node for the cloud-edge continuum. To do so, a state-of-the-art SoC platform with an application-grade RISC-V processor has been selected. An FPGA emulation of this platform is started on a development board available at CEI, and the hardware needed to integrate the CGRA is developed. A kernel module is written so that the CGRA accelerator may be used from within a Linux user process. This allows to take advantage of the application-class processor, by running Linux, and of the hardware acceleration provided by the CGRA. Finally, accelerator performance is evaluated both in bare-metal and Linux contexts, including a comparison with purely software solutions (i.e., without hardware acceleration).