Design and analysis of GDI based kogge stone adder for low power applications

In modern VLSI design, the demand for highspeed and energy-efficient arithmetic circuits isever-growing, particularly in low-power computing applications. The KoggeStone Adder(KSA) is widely recognized for its parallel-prefix architecture, offering reduced delaycompared to conventional adders. However, traditional KSA implementations suffer fromhigh power consumption and increased transistor count. To address this, we propose aGDI-based Kogge-Stone Adder, leveraging the Gate Diffusion Input (GDI) technique tooptimize power efficiency while maintaining computational accuracy. The proposed designsignificantly reduces power dissipation and transistor count by minimizing unnecessaryswitching activity and interconnect complexity. Performance evaluation using simulationtools demonstrates that the GDI-based KSA achieves notable improvements in terms ofpower consumption, propagation delay, and area efficiency compared to conventionalCMOS-based KSA implementations. This work provides a promising approach fordesigning high-performance, low-power arithmetic circuits suitable for energy-efficientapplications..