Optimized FFA-Based 3-Parallel Polyphase FIR Filter Using Modified Brent-Kung Adder and Booth Multiplier for VLSI Applications

Digital Signal Processing (DSP) plays a crucial role in biomedical applications, as well as in voice and image processing. Digital filters serve as fundamental building blocks for DSP applications, signal analysis, and estimation. With advancements in VLSI technology, the complexity of designing digital filters has been significantly reduced, enabling efficient on-chip architectures for DSP applications.Finite Impulse Response (FIR) filters, which have a finite-duration impulse response, are widely used in DSP systems due to their stability and linear-phase characteristics, in contrast to Infinite Impulse Response (IIR) filters that exhibit feedback and indefinite response. This paper proposes an efficient Fast FIR Algorithm (FFA)-based 3-parallel polyphase odd-length FIR filter design utilizing optimized arithmetic components to enhance performance. Instead of conventional adders and multipliers, the proposed design integrates two types of multipliers—Vedic and Booth multipliers—along with three types of adders—Ripple Carry Adder (RCA), Carry Look-Ahead Adder (CLA), and Brent-Kung Adder (BKA).To further optimize circuit complexity and improve efficiency, a modified Brent-Kung adder is introduced in place of the conventional Brent-Kung adder within the efficient 3-parallel polyphase FIR filter design. The proposed architecture is implemented using Xilinx and simulated with ModelSim software, demonstrating improved computational efficiency and reduced hardware complexity for VLSI applications.