LOW-POWER RETENTIVE TRUE SINGLE PHASE CLOCKED FLIP FLOP WITH REDUNDANT PRECHARGE FREE OPERATION

As digital systems improve, power consumption has become a critical limitation, especially with the rapid growth of battery-powered IoT devices. Flip-flops (FFs), essential components of digital circuits, contribute significantly to power usage. Therefore, reducing FF power consumption can substantially lower the overall power of digital systems. Voltage scaling is a promising technique for reducing power consumption, but it requires FFs capable of operating efficiently at both super-threshold and near-/sub-threshold voltages. The transmissiongate flip-flop (TGFF), widely used for its contention-free operation, is suitable for near-threshold applications. However, its large clock network and toggling internal nodes (CKN and CKI) lead to high power consumption, even with low data activity. Optimizing complementary clock signals can help reduce this power consumption. While several low-power, single-phase-clocked FFs have been proposed, challenges such as failure at low voltages or high precharge power remain