ITZO-Based Self-Aligned\nTop Gate Thin-Film Transistor\nwith Minimum Parasitic Capacitance for Long-Retention 2T0C DRAM

We developed a two-transistor, zero-capacitor (2T0C)\ngain-cell\nmemory featuring a self-aligned top-gate-structured thin-film transistor\n(TFT) for the first time. The proposed indium tin zinc oxide (ITZO)\nchannel-incorporated architecture was specifically engineered to minimize\nparasitic capacitance for achieving long-retention 2T0C memory operations.\nA typical 2T0C structure features five types of parasitic capacitances;\nhowever, the proposed SATG design effectively used an essential gate\ninsulator capacitance (<i>C</i><sub>OX</sub>) and reduced\nfour nonessential capacitances (<i>C</i><sub>WBL‑WWL</sub>, <i>C</i><sub>WWL‑SN</sub>, <i>C</i><sub>RWL‑SN</sub>, and <i>C</i><sub>RBL‑SN</sub>) to virtually zero. The ITZO-based 2T0C gain-cell memory achieved\na retention time >10,000 s owing to the extremely low off-current\n(2.33 × 10<sup>–18</sup> A/μm), superior positive-bias\nstability (0.71 V), and high saturation mobility [17.52 cm<sup>2</sup>/(V s)] of the optimized TFT structure. Our proposed memory with\nlong retention and high endurance is a promising solution for next-generation\n3D-integrated stacked dynamic random-access memories and defines a\nnew structural standard for future memory architectures.