Gate-Tunable Negative\nDifferential Resistance in WSe<sub>2</sub>/h-BN/Graphene Heterostructure

Negative differential resistance\n(NDR) devices show potential\nfor\nadvanced future computing technologies with deficient energy consumption,\nparticularly in multivalued logic computing due to multiple threshold\nvoltages. Here, we report an NDR phenomenon observed in a heterostructure\nof graphene (Gr), hexagonal boron nitride (h-BN), and tungsten diselenide\n(WSe<sub>2</sub>) in the negative gate voltage regime. In this structure,\nWSe<sub>2</sub> is employed as a channel material aligned with a dielectric,\nh-BN, while Gr acts as a floating gate. The investigation of temperature-dependent\nelectrical charge transport using the global gate allows for identifying\nthe tunneling process within a specific range of gate voltages. In\naddition, the electrical charge transport measurement demonstrates\nsignificant gate-tunable NDR behavior with a maximum peak-to-valley\ncurrent ratio of 7.2 at room temperature, which improved to 11.6 at\na temperature of 77 K. To the best of our knowledge, this is the unique\ndemonstration of NDR charge transport behavior in a single-channel\nWSe<sub>2</sub> field-effect transistor device. This feature promises\nmany applications, such as low-power logical circuits, memory, and\nhigh-frequency switching devices.