A 31-Segment Asymmetrical Cascaded Multilevel Inverter

The 31-level Asymmetrical Cascaded Multilevel Inverter used in this project provides commentary. Asingle stage sub multilevel converter unit and a complete bridge cascaded multilevel inverter connected ina cascaded manner form the foundation of the topology. Plans are in place for the input DC voltagesources of Vdc1–Vdc4 to be paired at 15 Vdc1, 30 Vdc2, 60 Vdc3, and 120 Vdc4 each. The powersemiconductor switches in the asymmetric cascaded multilevel inverter are controlled by a low frequencypulse width modulation method. A DC source feeds the DC link with a higher voltage. With aunidirectional power flow and a high frequency transformer processing up to 33% of the load power, theprimary DC link supplies the other, lower voltage dc links. A detailed presentation is made of the HFLsystem architecture, a nearest-level control, and an analysis of the power distribution among each dcconnection. Furthermore, employing HFL, comparisons with alternative multilevel topologies areperformed. The system analyses and uses the total harmonic in real time.