Synthesis and Efficient Design of Reversible Serial Adder Based on EPOE Expressions

The design of a low-cost self-control serial adder system is suggested in this project. The suggested circuit reduces the fixed inputs of sequential logic circuits by using EPOE expressions for the direct and compact design of sequential circuits. When it comes to energy-efficient calculations, reversibility is crucial. Common terms between the outputs are used as efficiently as possible to lower the quantum cost. The final circuit's quantum cost can be decreased by restricting the use of Toffoli gates larger than three inputs.