Study the Performance of Silicon-On-Insulator Based Junction Less Transistor Using MOS and FGMOS 6t-Sram Cells

In this research, a 6T SRAM cell comprises of two cross-coupled inverters and two access transistors was design and simulated using Sentaurus TCAD and Spice Simulator. The cross-coupled inverters are the memory part used to store the data. When the access transistors are turn ON, enabling the read/write operation. 6T SRAM using metal oxide semiconductor (MOS) and floating gate metal oxide semiconductor (FGMOS) of different node technologies at constant drain voltage (Vdd) of 0.35V were designed and simulated. Power dissipation and delay were computed for different technology nodes using MOS and FGMOS devices. It has been observed that 45nm technology node 6T SRAM cell demonstrated most optimized power dissipation as compared to 180nm, 90nm, and 65nm technology 6T-SRAM cells when we use MOS and FGMOS. In case of delay measurement, it was observed that device with FGMOS have most improved. This reduces the power dissipation, making the SRAM cell applicable for low power applications, and the use of FGMOS further decreases the power dissipation and delay of the 6T-SRAM cell.