Selection of modified carrier for Optimization Delay of Binary Coded Decimal(BCD)

Abstract: In digital systems the Binary Coded Decimal (BCD) representation acts or plays a vitalrole for exact decimal representing and processing are required. It is mainly useful in financialsectors. This paper draws a kind of novel approach in delay optimization in BCD addition byselecting or using modified carrier mechanism, which reduces the conventional carry propagationstructure without compromising accuracy with enhancing the speed. However while usingtraditional BCD arithmetic operations, particularly addition, are prone to higher propagation delaysdue to carry generation and correction mechanisms. To reduce or minimize the overall critical pathdelay the BCD operation works by incorporating methods like carry- skip, carry-look ahead orhybrid carry-select technique. The reconstructed results indicate the standard benchmark circuitsillustrate the noteworthy development in computation time and power efficiency. The alteredcarrier logic ensures the fast decimal arithmetic processing which makes it accurate and highlysuitable for real-time embedded systems and low-latency computing environments. The paperfurther discusses the trade-offs between complexity, area and power in achieving delayoptimization providing a comprehensive evaluation of the proposed technique.

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2025-07-15
DOI
https://doi.org/10.5281/zenodo.15903683
Primary Topic
Low-power high-performance VLSI design
Type
article
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article

Selection of modified carrier for Optimization Delay of Binary Coded Decimal(BCD)

Zenodo (CERN European Organization for Nuclear Research)
Low-power high-performance VLSI design
article

Selection of modified carrier for Optimization Delay of Binary Coded Decimal(BCD)

article en

Abstract

Abstract: In digital systems the Binary Coded Decimal (BCD) representation acts or plays a vitalrole for exact decimal representing and processing are required. It is mainly useful in financialsectors. This paper draws a kind of novel approach in delay optimization in BCD addition byselecting or using modified carrier mechanism, which reduces the conventional carry propagationstructure without compromising accuracy with enhancing the speed. However while usingtraditional BCD arithmetic operations, particularly addition, are prone to higher propagation delaysdue to carry generation and correction mechanisms. To reduce or minimize the overall critical pathdelay the BCD operation works by incorporating methods like carry- skip, carry-look ahead orhybrid carry-select technique. The reconstructed results indicate the standard benchmark circuitsillustrate the noteworthy development in computation time and power efficiency. The alteredcarrier logic ensures the fast decimal arithmetic processing which makes it accurate and highlysuitable for real-time embedded systems and low-latency computing environments. The paperfurther discusses the trade-offs between complexity, area and power in achieving delayoptimization providing a comprehensive evaluation of the proposed technique.

Zenodo (CERN European Organization for Nuclear Research)
Biju Patnaik University of Technology (IN)
Openalex Percentile: Top 56%
Low-power high-performance VLSI design
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