GENETIC ALGORITHM FOR LEAKAGE REDUCTION THROUGH IVC USING VERILOG

VLSI design constraints are always area, power and delay. Power consumption of VLSI has become a leading design concern with the growth of complexity and density. Leakage power reduces battery life for the entire portable battery operated device such as mobile phones, laptop and camcoder and so on. Reduction of leakage power is of peak concern in the present trend of nanotechnology. Many techniques have been projected to reduce the leakage power consumption, but most of these approaches require the process technology support. Input Vector Control is one of the approaches used for static power reduction in standby mode. Leakage in a circuit depends on input vector applied at primary inputs due to stack effect. Minimum leakage vector is the input vector to which a circuit can suggest a minimum leakage for a certain set of test patterns. This paper presents Minimum Leakage Vector for various test circuits using genetic algorithm. The algorithm is simulated in Verilog HDL to acquire MLV. Results explore that heuristic approaches can be considered as better algorithms in finding optimum solution. Another improvement begins during simulation is that implementation of algorithm in HDL converges in lesser number of iterations with runtime savings compared to random search method.