AI-OPTIMIZED RECONFIGURABLE COMPUTING ARCHITECTURES FOR ADAPTIVE WORKLOAD ACCELERATION IN HETEROGENEOUS SYSTEMS-ON-CHIP: A UNIFIED FRAMEWORK COMBINING DYNAMIC PARTIAL RECONFIGURATION, HARDWARE-AWARE SCHEDULING, AND SELF-ADAPTIVE RESOURCE MANAGEMENT

The advent of artificial intelligence (AI) and the proliferation of workload-diverse edge and cloud platforms necessitate a rethinking of traditional system-on-chip (SoC) designs. This paper proposes a unified AI-optimized reconfigurable computing architecture that leverages dynamic partial reconfiguration (DPR), hardware-aware task scheduling, and self-adaptive resource management. The proposed framework enables real-time optimization of computing workloads across heterogeneous SoCs, significantly improving system throughput, energy efficiency, and task adaptability. Our design illustrates a scalable model suitable for various AI-centric applications while maintaining computational elasticity and minimizing hardware wastage.