VHDL IMPLIMENTATION OF PARALLEL MULTIPLIERS BASED ON MODIFIED BOOTH ALGORITHM

Multipliers are playing a vital role in DSP and Neural Networks applications. Many methods have been introduced to work on multipliers that offer high speed, less power consumption and reduced area. Booth Algorithm demonstrates an efficient way of signed binary multiplication. In this paper, physical design of radix4,radix-8 and radix16 booth multiplier for signed multiplication is presented with an aim to improve the performance metrics such as power, area and delay. The performance of radix4, radix-8 booth multiplier is compared with the radix-16 booth multiplier. Low power consumption and small area are some of the most important criteria for design of any high performance systems. So in this paper the best solution to the problem is determined by designing a high speed multiplier chiefly booth multiplier which reduces the number of flip flops and memory size in the design circuitry as compared to conventional serial multiplier. Then implementation of a calculator using booth multiplier and several other operational modules is done using codes written in VHDL language using ISE XILINX 14.7 and simulated in MODEL SIM.