Optimized Majority Logic Approximate Adders and Multipliers for Low-Power Computing

Approximate arithmetic circuits based on CMOS technology have been widely explored for their potential in low-power and error-tolerant computing. Various designs of approximate adders and multipliers for both fixed-point and floating-point arithmetic have been proposed. As a key paradigm in nanoscale technologies, approximate computing enables energy-efficient arithmetic operations while tolerating computational errors. Majority logic (ML), particularly its fundamental component—the 3-input majority voter—has been extensively utilized in digital circuit design across emerging technologies. In this work, we propose a one-bit approximate full adder based on majority logic, along with multi-bit approximate full adder designs. Additionally, we explore their application in Quantum-Dot Cellular Automata (QCA) as a case study. The proposed designs are evaluated based on hardware efficiency metrics, including delay and area, as well as error performance. Comparative analysis with existing circuits from the literature demonstrates that the optimized designs achieve superior performance. Furthermore, we highlight the significance of Finite Impulse Response (FIR) filters in signal processing and communication. Since FIR filter performance heavily relies on adder and multiplier units, our proposed approximate arithmetic circuits offer potential improvements in power and area efficiency for such applications.