Characterising RFET-based standard cells for circuit synthesis - Supplementary Material

Supplementory Material for the Diploma Thesis "Characterising RFET-based standard cells for circuit synthesis - Supplementary Material" including thesis sources, software and dataset Abstract: Reconfigurable field-effect transistors (RFETs) are a device technology that is both in active research and early experimental industrial production. They feature (1) reconfiguration to either P- or N-type conductivity at runtime (2) multiple gates on a single device forming a wired AND function and (3) possible integration with standard CMOS production technology. This makes RFETs well suited for applications in IP protection and low-energy computing and shows potential in other areas such as neuromorphic and asynchronous computing. For practical circuit design, the characteristics of standard cells have to be made available to synthesis tools.\Gls{liberty} files are an industry standard for this purpose which is supported by a variety of tools. This work presents a fully automated workflow for creating and characterizing RFET-based standard cells from arbitrary combinational logic functions and creating a Technology Library in form of a \gls{liberty} file.It combines algorithmic design space exploration and characterization of logic cells using a formal approach.Automating this workflow is important as the features of RFETs facilitate a multitude of ways to implement a logic function. These implementations differ in their characteristics making some of them preferable in certain applications.The resulting \gls{liberty} files have been successfully used with synthesis tools \gls{genus} and Yosys/ABC to synthesize mapped netlists for combinational benchmark circuits,allowing us to speed up design iterations and compare performance in real world designs. This work also shows limitations of the \gls{liberty} format and proposes solutions for handling typical features of RFET-based circuits, like pass-gate transistors and reconfiguration requiring an input signal and its inverse. Where appropriate, multiple alternative solutions are proposed for (1) keeping compatibility with existing synthesis tools and (2) extending the format to include additional information to fully utilize RFETs. Further steps are discussed on how to expand the presented workflow to more complex cells with sequential behaviour and multiple outputs.