Energy Efficiency and Fault Tolerance for Spiking and Deep Neural Networks

Neural Network (NN) algorithms have achieved state-of-the-art accuracy in various data analytic applications, such as object recognition, healthcare, and autonomous driving. Therefore, deploying advanced NNs like deep neural networks (DNNs) and spiking neural networks (SNNs) to resource- and energy-constrained embedded systems is important for improving productivity of human life through higher efficiency, lower latency, as well as better security and privacy. However, deploying embedded NN systems is very challenging since NNs are memory- and compute-intensive, thereby requiring significant memory and energy consumption, which limit their applicability. Current solutions still face energy efficiency issues due to high memory access energy and incur significant memory and energy overheads for adapting to dynamically-changed environments, which make the learned knowledge obsolete and degrade the run-time accuracy. Additionally, current SNN-based systems do not mitigate the hardware-induced faults (e.g., approximation errors, permanent faults, and transient faults). Toward this, our research develops a novel methodology that employs cross- layer hardware- and software-level techniques for improving energy efficiency and fault tolerance of spiking and deep neural networks. We improve DNN- and SNN-based systems by optimizing the off-chip memory (DRAM) access energy, as it dominates the total system energy. Then, we enhance the SNN-based systems to efficiently adapt to dynamic environments through a lightweight unsupervised continual learning mechanism. Furthermore, we improve the fault tolerance of SNN- based systems against hardware-induced faults. Specifically, we mitigate approximation errors and permanent faults by employing fault-aware training and efficient fault-aware mapping without retraining. We also mitigate transient faults (i.e., soft errors) by employing weight bounding and neuron protection. To support these fault mitigation techniques, we propose lightweight hardware enhancements. All these techniques are integrated into our novel methodology to provide a judicious and synergistic design approach for enabling energy-efficient and fault-tolerant NN-based systems in diverse operating conditions, which is crucial for resource- and energy-constrained embedded applications.