Advancing Processing-in-Memory Through Integration of Emerging Non-Volatile Devices and Novel Data Representation

The disproportionate improvement in speed of microprocessors over memory speed in modern computing devices led to the memory wall problem, which has motivated researchers to develop Processing-in-Memory (PiM) architectures to bring computation closer to or inside memory, resulting in a significant reduction in energy consumption during memory-intensive computations. This substantial reduction in energy consumption has motivated researchers to explore various methods that can be integrated into Processing-in-Memory (PiM) architectures to achieve further energy efficiency. One such method is innovative data representation, as different data representations may exhibit varied complexities across domains, with some operations becoming simpler (e.g., residue coded, frequency domain, log scale) while others may grow in complexity. One such innovative data representation is temporal encoding, which allows a single gate to perform multibit operations between two temporally encoded data streams, enabling massive computation with area and energy-efficient computing units. This temporal data representation enables efficient computing, utilizing straightforward logic gates, and makes a compelling argument that combining the strengths of time-domain computation and PiM offers a promising path to develop hardware accelerators tailored for computation and memory-intensive machine learning (ML) tasks, particularly suited for the Internet of Things (IoT) at the edge. Researchers have explored various memory devices, including conventional SRAM and DRAM, as well as emerging non-volatile magnetic and resistive memory technologies, to build PiM architectures. This thesis capitalizes on the potential of emerging magnetic racetrack memories to establish a comprehensive Temporal Processing-in-Memory architecture, designed to accelerate tree traversal-based Machine Learning algorithms. Our approach utilizes magnetic skyrmion-based temporal memory to encode analog input data into time-coded streams during memory write operations, minimizing data conversion costs. Additionally, we develop all the key components of the proposed architecture, such as the non-volatile comparator and majority voter, employing a skyrmionic racetrack. This proposed architecture facilitates parallel processing of sequential input streams, eliminating the costly Non-Uniform Memory Access (NUMA) patterns inherent in tree-traversal algorithms. We then further address the fundamental precision challenge in analog computing by developing a novel polynomial bit-spliced arithmetic approach that mathematically decomposes high-precision operations into multiple lower-precision computations processed in parallel. Our architecture achieves 16-bit equivalent accuracy while using only 4-bit analog-to-digital converters. This technique reduces the ADC energy by 8× compared to conventional approaches and enables a 30% reduction in overall energy consumption while maintaining accuracy within 0.5% of the digital implementations. Our mixed-precision processing-in-memory architecture demonstrates that high-precision analog computing is viable without the exponential hardware costs traditionally associated with high precision.