ASIC and FPGA Implementation of an Adaptive Convolutional Encoder and Viterbi Decoder

This paper introduces a novel approach and proposes an enhanced microarchitecture for implementing a high-frequency convolutional encoder and Viterbi decoder using both application-specific integrated circuit (ASIC) and field programmable gate array (FPGA) technologies. The design of the encoder and decoder is adaptive and capable of processing variable lengths of input bit streams in a message signal. This means our circuit exhibits message width independence, resulting in a constant effective delay per bit for the proposed implementation. Furthermore, an adaptive (2, 1, 3) convolutional encoder is developed to allow customization of connection vectors. The circuit implementation utilizes conventional logic gates and sequential circuit elements, ensuring complete tolerance to single-bit errors and a satisfactory level of multi-bit error tolerance. To evaluate the proposed design, Cadence generic process design kits 45 nm technology (GPDK45) are employed to synthesize the circuit, providing area, power, and timing reports for further analysis. The proposed Viterbi decoder can operate up to a frequency of 580.046 MHz and consumes 632.358 µm² area with a power dissipation of 68.0313 <i>µ</i>W. The circuit implementation is validated using Xilinx FPGA boards through Xilinx Vivado 2020.2 across diverse product families and operating frequencies. The obtained results are meticulously compared to determine the most suitable FPGA for different frequency ranges. It's crucial to highlight that all results presented in this paper are validation-based, meaning they were generated using software tools.