Selection of modified carrier for Optimization Delay of Binary Coded Decimal(BCD)

Abstract: In digital systems the Binary Coded Decimal (BCD) representation acts or plays avital role for exact decimal representing and processing are required. It is mainly useful infinancial sectors. This paper draws a kind of novel approach in delay optimization in BCDaddition by selecting or using modified carrier mechanism, which reduces the conventional carrypropagation structure without compromising accuracy with enhancing the speed. However whileusing traditional BCD arithmetic operations, particularly addition, are prone to higherpropagation delays due to carry generation and correction mechanisms. To reduce or minimize the overall critical path delay the BCD operation works by incorporating methods like carry- skip, carry-look ahead or hybrid carry-select technique. The reconstructed results indicate the standard benchmark circuits illustrate the noteworthydevelopment in computation time andpower efficiency.The alteredcarrier logic ensures the fast decimal arithmetic processing whichmakes it accurate and highly suitable for real-time embedded systems and low-latencycomputing environments.The paper further discusses the trade-offs between complexity, area andpower in achieving delay optimization providing a comprehensive evaluation of the proposedtechnique.

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Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2025-07-12
DOI
https://doi.org/10.5281/zenodo.15869403
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
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article

Selection of modified carrier for Optimization Delay of Binary Coded Decimal(BCD)

Zenodo (CERN European Organization for Nuclear Research)
Low-power high-performance VLSI design
article

Selection of modified carrier for Optimization Delay of Binary Coded Decimal(BCD)

article en

Abstract

Abstract: In digital systems the Binary Coded Decimal (BCD) representation acts or plays avital role for exact decimal representing and processing are required. It is mainly useful infinancial sectors. This paper draws a kind of novel approach in delay optimization in BCDaddition by selecting or using modified carrier mechanism, which reduces the conventional carrypropagation structure without compromising accuracy with enhancing the speed. However whileusing traditional BCD arithmetic operations, particularly addition, are prone to higherpropagation delays due to carry generation and correction mechanisms. To reduce or minimize the overall critical path delay the BCD operation works by incorporating methods like carry- skip, carry-look ahead or hybrid carry-select technique. The reconstructed results indicate the standard benchmark circuits illustrate the noteworthydevelopment in computation time andpower efficiency.The alteredcarrier logic ensures the fast decimal arithmetic processing whichmakes it accurate and highly suitable for real-time embedded systems and low-latencycomputing environments.The paper further discusses the trade-offs between complexity, area andpower in achieving delay optimization providing a comprehensive evaluation of the proposedtechnique.

Zenodo (CERN European Organization for Nuclear Research)
Biju Patnaik University of Technology (IN)
Openalex Percentile: Top 57%
Low-power high-performance VLSI design
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Selection of modified carrier for Optimization Delay of Binary Coded Decimal(BCD) · Zenodo (CERN European Organization for Nuclear Research) (2025) | TGRS Research Map | TGRS