Hyper-Precision Fault Mapping in Reconfigurable Logic via Adaptive Stochastic Resonance and Bayesian Inference

**Abstract:** This paper presents a novel methodology for high-precision fault mapping in Field-Programmable Gate Arrays (FPGAs) leveraging Adaptive Stochastic Resonance (ASR) coupled with Bayesian Inference. While traditional Built-In Self-Test (BIST) schemes often suffer from limited spatial resolution and susceptibility to noise, our approach dynamically amplifies weak fault signals through ASR while simultaneously refining fault localization probabilities using Bayesian updates based on test response patterns. This combination achieves a 10-fold improvement in fault mapping fidelity compared to conventional techniques in complex FPGA architectures, enabling more rapid and targeted repair strategies. The methodology is immediately commercializable for FPGA manufacturers and users seeking enhanced diagnostics and reliability.

Institutions

Publication Details

Journal
Zenodo (CERN European Organization for Nuclear Research)
Published
2025-08-11
DOI
https://doi.org/10.5281/zenodo.16790963
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Hyper-Precision Fault Mapping in Reconfigurable Logic via Adaptive Stochastic Resonance and Bayesian Inference

Zenodo (CERN European Organization for Nuclear Research)
VLSI and Analog Circuit Testing
article

Hyper-Precision Fault Mapping in Reconfigurable Logic via Adaptive Stochastic Resonance and Bayesian Inference

article en

Abstract

**Abstract:** This paper presents a novel methodology for high-precision fault mapping in Field-Programmable Gate Arrays (FPGAs) leveraging Adaptive Stochastic Resonance (ASR) coupled with Bayesian Inference. While traditional Built-In Self-Test (BIST) schemes often suffer from limited spatial resolution and susceptibility to noise, our approach dynamically amplifies weak fault signals through ASR while simultaneously refining fault localization probabilities using Bayesian updates based on test response patterns. This combination achieves a 10-fold improvement in fault mapping fidelity compared to conventional techniques in complex FPGA architectures, enabling more rapid and targeted repair strategies. The methodology is immediately commercializable for FPGA manufacturers and users seeking enhanced diagnostics and reliability.

Zenodo (CERN European Organization for Nuclear Research)
Freed–Hardeman University (US)
Openalex Percentile: Top 52%
VLSI and Analog Circuit Testing
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Hyper-Precision Fault Mapping in Reconfigurable Logic via Adaptive Stochastic Resonance and Bayesian Inference · Zenodo (CERN European Organization for Nuclear Research) (2025) | TGRS Research Map | TGRS