Design of Read, Write Separation based low voltage 6T SRAM Memory Array

This research investigates the performance optimization of a 6T SRAM cell design in 45nm technologies. Focused on reducing both power consumption, access time and area the study utilizes microwind tools for transient and DC analysis. Speed is the biggest advantage of SRAM. As long as power is supplied, SRAM retains data. Also, since it does not require time-consuming refresh cycles, SRAM enables fast data access and offers lower latency. Due to the capacitor is used in DRAM, which is more power consumed and uses large refreshing circuits. This problem is avoided in SRAM memory cell. Hence it's essential to possess energy- efficient present circuit static memory which focuses on optimizing delay and power. .The olden days SRAM cell consumed more power and produces more delay. To decrease the power consumption and time, the introduced 6T SRAM cell separates read and write operation and. The proposed SRAM array is designed using micro wind (45nm) and the power measured as 281mW, and delay is 18.2 nsec.