FSM-Based Implementation of the Lempel-Ziv-Welch (LZW) Data Compression Algorithm Using Verilog HDL

This project presents a Register Transfer Level (RTL) implementation of the Lempel-Ziv-Welch (LZW) lossless data compression algorithm using Verilog HDL, structured around a Finite State Machine (FSM). Designed and simulated in ModelSim, the system compresses ASCII character sequences by dynamically building a dictionary of repeated substrings, outputting compressed binary codes in real-time. The FSM governs six key operational states—IDLE, INPUT, SEARCH, ADD, OUTPUT, and DONE—ensuring sequential, deterministic control over dictionary management and code emission. A simulation-based testbench verifies the functional correctness of the compressor, demonstrating accurate pattern matching, dynamic dictionary updates, and stable output transitions under clocked conditions. This behavioral-level design provides a robust platform for understanding algorithm-to-hardware translation and serves as a scalable base for future extensions like pipelining, hardware deployment (e.g., on FPGAs), or decompression logic integration.