An Efficient Pipelined and Stage-Folded Architectures for High-Performance Polar Encoding-Decoding Systems

Polar codes are powerful error-correcting codes that are now widely used in communication systems like 5G due to their ability to achieve high reliability and speed. However, traditional designs for polar encoders and decoders often suffer from high delay, large hardware usage, and limited processing speed. To address these issues, this paper presents an efficient architecture using pipelining and stage-folding techniques to improve both the speed and resource usage of polar encoding and decoding. The pipelined structure allows multiple data blocks to be processed at the same time, while the stage-folded design reuses hardware components, reducing area and power consumption. This combination results in faster processing, lower power usage, and a more compact design, making it ideal for real-time and energy-constrained systems such as mobile devices, IoT, and wireless networks.