Decoder Reduction Approximation Scheme For Booth Multipliers Using Brent-Kung Adder

Abstract: This work reveals a new approximation method that uses Booth multipliers to reduce the amount of error produced while reducing the number of decoders in the design to increase computational efficiency. To make it more efficient, the design forms part of the Brent-Kung Adder which captures the benefits of its parallel prefix structure in achieving low propagation delay and improvement in scalability. The 16-bit BD16.4 multiplier together with the Brent-Kung Adder thrives in performance and accuracy compared to conventional logarithmic and higher-radix multipliers. Further, its 8-bit counterparts have shown magnitudes of improvement against the existing logarithmic designs rendering them very appropriate for resource tamed applications. Extensive evaluations like neural network inference tests prove that these approximate multipliers with the Brent-Kung Adder deliver high accuracy, reduced hardware complexity, and significant savings in Power-Delay-Product. This will close the gap between high-speed computation and energy-efficient hardware design, making it a great solution for modern VLSI implementations.