DESIGN AND VERIFICATION OF APB PROTOCOL

This paper presents a parameterizable Verilog implementation of the AMBA 3 Advanced Peripheral Bus (APB) protocol, comprising a master finite-state machine (FSM) and a configurable slave module. The master FSM cleanly sequences the two-phase SETUP and ACCESS transactions, generating the requisite control signals (PSELx, PENABLE, PWRITE, PADDR) and handling the slave’s PREADY handshake. The slave incorporates an internal memory array, a programmable wait-state counter to model peripheral latency, and error-detection logic (PSLVERR) on a designated fault address. We validate functional correctness through exhaustive simulation—covering zero-wait, multi-wait, boundary, and error-response scenarios—and confirm protocol compliance and data integrity. Post-synthesis results on Xilinx Vivado 2020.2 demonstrate minimal logic utilization (< 1%), positive timing slack at 100 MHz, and ultralow dynamic power (< 2 mW). In-code parameters for data width, address width, and wait cycles ensure seamless adaptation to diverse system-on-chip environments. This work delivers a lightweight, low-power APB IP core suitable for modern SoC peripheral integration.