FPGA Based Convolution Accelerator For Image Recognition

Abstract: The use of machine learning based applications has become widespread in today’s era. Many CNN based implementation require high computational power and consumes time. CNNs are the base for any machine learning or neural network process. They are developed primarily using GPUs (Graphical Processing Units) that require very high-power consumption and are also expensive. The process is either sequential or pipelined and hence requires more computation time. With the usage of FPGAs, where the process is parallelized increases the efficiency of the process, thus reduces the power consumption compared to that of GPUs. Image recognition is the most commonly used machine learning application. Any machine learning application would involve an image recognition step. Hence developing of optimal energy consuming and low-cost models for image recognition is the need of the moment. FPGAs reconfigurability and its hardware parallelism provides flexibility and high performance with less processing power. These advantages of FPGAs can be utilized to generate an energy efficient and low-cost model of a CNN accelerator for image recognition. This helps to deploy the CNN models in low-end and battery-operated devices.