Field Effect Transistor based Driver Circuits using Annealing Techniques

Of the four fundamental microprocessor processes, division is thought to be the slowest and most challenging. This paper presents an unprecedented division algorithm using a new approach of simulated annealing algorithm. While the traditional methods use random values to attain the target value, a heuristic function is introduced to identify the global and local optimum value. A revised temperature schedule is also presented in order to compute global maxima and minima more quickly. Because a novel goal-based temperature is introduced, the suggested simulated annealing algorithm outperforms the most well-known simulated annealing technique currently in use for smooth energy landscapes. In order to drastically cut down on the delay of the suggested divider circuit, the suggested division algorithm calculate the current partial remainder and quotient bits simultaneously in each iteration. Furthermore, the existing best Divider circuit requires three operations per iteration, while the suggested one only requires two. The suggested divider circuit outperforms the most well-known modern FPGA-based divider circuit by 36.17% and 44.67%, respectively, in terms of LUTs and delay for a 256 by 128 bit division.