Investigation of logic errors in memristive crossbars for computing-in-memory

Valence Change Mechanism (VCM) redox-based Resistive Random Access Memories (ReRAM) are possible candidates to replace CMOS-based SRAM in data storage applications. These devices offer non-volatility, scalability, and an improved reliability, making them well-suited for data storage systems. The inclusion of filamentary VCM-ReRAM cells with Complementary Metal-Oxide Semiconductor (CMOS) transistors in 1T-1R crossbar arrays further enhances the device control, enabling the integration of large-scale resistive architectures. Beyond pure data storage, resistive switching memories are suitable for Computing-in-Memory (CIM) applications, including Boolean logic and arithmetic operations. However, resistive logic CIM is still in development as the device variability and integration challenges are limiting a large-scale experimental verification. Therefore system-level simulations are exploited to predict the performance of resistive computing systems. While energy consumption and latency are straightforward to evaluate, the reliability and error probabilities in resistive CIM systems remain less understood. Due to the inherent device variability, demonstrating a single logic gate is insufficient to guarantee the reliability of large-scale systems involving thousands of operations. This thesis tries to address this gap by comprehensively investigating singlegate logic operations in 1T-1R CMOS/ReRAM crossbars and through a combination of experimental studies and variability-aware simulations. The work examines two key branches of resistive logic: readout-based and switching-based operations. Readout-based logic relies on the sensing of resistive states as analog quantities and classifying them as digital values. Its reliability is limited by the accuracy of state sensing and the overlap of resistive distributions. Switching-based logic, in contrast, is based on a conditional state transition through an input-dependent voltage divider. Here, the reliability is determined not only by the resistive state variability but also by the stochastic nature of the switching mechanism. Therefore, both logic concepts require individual approaches in order to estimate their error proneness. By systematically analyzing both concepts, this thesis proposes methodologies to evaluate and improve the reliability of both types and extrapolates the findings to more complex CIM systems. Building on previous single-gate demonstrations, the thesis provides comprehensive experimental measurements of co-integrated 1T-1R crossbars and variability-aware circuit simulations to quantify the error probabilities of single logic gates. Furthermore, it identifies critical operational parameters to improve the reliability. On the example of a full adder, a hybrid approach is discussed which combines readout-based and switching-based logic in order to optimize the reliability. These methodologies can be adapted to other resistive-based logic gates and may be extended beyond filamentary VCM devices to explore a broader range of resistive technologies.