SIRIUS fast beam orbit interlock system

Insertion devices (IDs) are currently being installed at the SIRIUS storage ring to provide photon beams for upcoming high-brilliance beamlines. A fast orbit distortion detection system is imperative to safeguard critical vacuum chambers located near the straight sections of the IDs. In November 2023, an in-house Delta undulator was successfully installed, and a fast orbit interlock protection system has been in place, utilizing BPMs and the timing system's infrastructure. A dedicated position and angle calculation is implemented in FPGA and operates at a 6 kHz rate in the BPM processing electronics. A timing receiver board at the BPM uTCA crate acts as a bridge between orbit distortion detection and the timing system’s event generator (EVG), which sends an interlock signal to the LLRF controller. The main purposes of this work are to provide details about a new full-duplex timing network implementation, to discuss the main requirements of the orbit interlock, and to present measured performance results. Additionally, in pursuit of enhancing system reliability, post-mortem analysis and ongoing implementation proposals will also be presented.

Publication Details

Journal
JACOW
Published
2024-12-18
DOI
https://doi.org/10.18429/jacow-ibic2024-thp29
Primary Topic
Particle Accelerators and Free-Electron Lasers
Type
article
Field-Weighted Citation Impact
0.00
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article

SIRIUS fast beam orbit interlock system

JACOW
Particle Accelerators and Free-Electron Lasers
article

SIRIUS fast beam orbit interlock system

article en

Abstract

Insertion devices (IDs) are currently being installed at the SIRIUS storage ring to provide photon beams for upcoming high-brilliance beamlines. A fast orbit distortion detection system is imperative to safeguard critical vacuum chambers located near the straight sections of the IDs. In November 2023, an in-house Delta undulator was successfully installed, and a fast orbit interlock protection system has been in place, utilizing BPMs and the timing system's infrastructure. A dedicated position and angle calculation is implemented in FPGA and operates at a 6 kHz rate in the BPM processing electronics. A timing receiver board at the BPM uTCA crate acts as a bridge between orbit distortion detection and the timing system’s event generator (EVG), which sends an interlock signal to the LLRF controller. The main purposes of this work are to provide details about a new full-duplex timing network implementation, to discuss the main requirements of the orbit interlock, and to present measured performance results. Additionally, in pursuit of enhancing system reliability, post-mortem analysis and ongoing implementation proposals will also be presented.

JACOW
Industry, innovation and infrastructure
Openalex Percentile: Top 70%
Particle Accelerators and Free-Electron Lasers
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