A NOVEL PROCESSOR ARCHITECTURE IMPLEMENTING THE STACKED ERROR DIFFUSION ALGORITHM AND ITS ZYNQ-BASED REALIZATION

Digital halftoning reproduces continuous-tone images using patterns of black and white dots, while multitoning extends this concept by incorporating inks with intermediate intensities. These techniques are extensively utilized in the printing industry to accommodate the limited range of inks available in printers. Stacked error diffusion is a high-quality multitoning algorithm that adheres to the blue-noise dithering standard. This thesis research studies the potential parallelism inherent in the algorithm and introduces the design of a novel processor architecture optimized for efficient execution. The architecture is realized on an FPGA development board featuring a Zynq SoC. Additionally, the hardware prototype can also run a software implementation of the algorithm, leveraging the ARM CPU within the SoC. Test results confirmed both the functional correctness of the processor architecture and its substantial acceleration capability.