A 16-bit 10-GS/s DAC Achieving >65-dBc SFDR and <–75-dBc IM3 up to the Nyquist in 28-nm CMOS

This article presents an approach to mitigating both current source unit deviations and inter-symbol interference (ISI) non-linearities in Nyquist current-steering digital-to-analog converters (DACs). This approach enables switching-activity-controlled data-weighted-averaging (SAC-DWA) with 50% redundant cells by exploiting the input frequency range and the time-domain randomized element transition rate (ETR), leading to an input-independent switching activity. Utilizing SAC-DWA, a 16-bit 10-GS/s DAC is designed in 28-nm CMOS and mounted in a BGA package. In this DAC, the proposed SAC-DWA decoder is implemented in an overflow-detection-based low-complexity state machine to achieve ultra-high speed at 10 GS/s. In addition, a 1-D merged array placement is adopted to reduce the IR-drop mismatches between the segments of the most and least significant bits. Measurement results show that this DAC achieves spurious-free dynamic range (SFDR) >70 dBc up to 2.86 GHz and SFDR >65 dBc with third-order intermodulation distortion (IM3) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lt -75$</tex-math> </inline-formula> dBc over the entire Nyquist band.