High-Performance\nDual-Gate Transistors Based on Aligned\nCarbon Nanotubes

Aligned carbon nanotubes (A-CNTs), with atomic-scale\nthickness\nand ultrahigh carrier mobility, hold promise for constructing future\nsub-1 nm node integrated circuits (ICs) with higher speed and lower\npower consumption. However, the fabricated A-CNT transistors often\nsuffer from the disorder of high-density CNT, which degrade the off-characteristic\ndeviating significantly from theoretical values. Introducing a dual-gate\n(DG) configuration can provide higher gate control efficiency compared\nto conventional single-gate (SG) transistors and is expected to enhance\nthe overall performance of A-CNT transistors. However, the reported\nA-CNT dual-gate field-effect transistors (DG-FETs) still exhibit nonideal\nswitching behavior, and systematic exploration and optimizations for\nconstructing high-performance A-CNT DG structures have been lacking\nso far. In this work, we conducted a detailed study on the matching\nissues between the top-gate (TG) and bottom-gate (BG) stacks. By optimizing\nthe gate metal materials and dielectric layer thickness, we enabled\n20 nm channel A-CNT DG-FETs to achieve leading switching characteristics,\nincluding an on-state current density (I<sub>on</sub>) of up to 1.47\nmA/μm, a peak transconductance (G<sub>m</sub>) of 2 mS/μm,\na subthreshold slope (SS) as low as 83 mV/decade, and a current on/off\nratio of 10<sup>6</sup>. This study provides critical experimental\nguidance for constructing outstanding A-CNT DG-FETs at advanced technology\nnodes to compete with cutting-edge silicon-based chips and is also\nvalid for two-dimensional channels.