Low Contact\nResistance WSe<sub>2</sub> <i>p</i>‑Type Transistors\nwith Highly Stable, CMOS-Compatible Dopants

High\ncontact resistance has been a bottleneck in developing\nhigh-performance\ntransition-metal dichalcogenide (TMD) based <i>p</i>-type\ntransistors. We report degenerately doped few-layer WSe<sub>2</sub> transistors with contact resistance as low as 0.23 ± 0.07 kΩ·μm\nper contact by using platinum(IV) chloride (PtCl<sub>4</sub>) as the <i>p</i>-type dopant, which is composed of ions compatible with\nthe complementary metal-oxide-semiconductor (CMOS) fabrication process.\nTop-gated devices with a gate length of 200 nm showed good switching\nbehaviors, implying that the dopant diffusion into the gate stack\nis not significant. The devices showed nearly identical performance\nafter being kept in air for 86 days without any encapsulation while\nretaining the degenerately doped states at 78 K with pressure lower\nthan 10<sup>–5</sup> Torr, highlighting the stability of the\ndopants. The presented method sets forth the availability of highly\nstable methods for pattern doping the transistors with a thinned Schottky\nbarrier width for low contact resistance devices.

Publication Details

Journal
Figshare
Published
2024-10-18
DOI
https://doi.org/10.1021/acs.nanolett.4c02948.s001
Primary Topic
2D Materials and Applications
Type
article
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article

Low Contact\nResistance WSe2 p‑Type Transistors\nwith Highly Stable, CMOS-Compatible Dopants

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2D Materials and Applications
article

Low Contact\nResistance WSe2 p‑Type Transistors\nwith Highly Stable, CMOS-Compatible Dopants

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Abstract

High\ncontact resistance has been a bottleneck in developing\nhigh-performance\ntransition-metal dichalcogenide (TMD) based <i>p</i>-type\ntransistors. We report degenerately doped few-layer WSe<sub>2</sub> transistors with contact resistance as low as 0.23 ± 0.07 kΩ·μm\nper contact by using platinum(IV) chloride (PtCl<sub>4</sub>) as the <i>p</i>-type dopant, which is composed of ions compatible with\nthe complementary metal-oxide-semiconductor (CMOS) fabrication process.\nTop-gated devices with a gate length of 200 nm showed good switching\nbehaviors, implying that the dopant diffusion into the gate stack\nis not significant. The devices showed nearly identical performance\nafter being kept in air for 86 days without any encapsulation while\nretaining the degenerately doped states at 78 K with pressure lower\nthan 10<sup>–5</sup> Torr, highlighting the stability of the\ndopants. The presented method sets forth the availability of highly\nstable methods for pattern doping the transistors with a thinned Schottky\nbarrier width for low contact resistance devices.

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Low Contact\nResistance WSe<sub>2</sub> <i>p</i>‑Type Transistors\nwith Highly Stable, CMOS-Compatible Dopants · Figshare (2024) | TGRS Research Map | TGRS