Development of a Space Computer - A Low Risk Approach to Control and Data Processing Applications in Small Satellites

In early 1991, Honeywell delivered three RH-1 750A based flight computers to complete the AST III program in support of a Phillips Laboratory Autonomous Navigation Demonstration Satellite. The delivery was significant for the following reasons: it was the first delivery of a space qualified RH-1750A computer, the RH-1750 Multi-Chip Module (MCM) was transitioned from a research and development effort to a B-level flight part, and, design to delivery of the first flight unit was accomplished in only 16 months. The AST III program consists of several sequential efforts which will demonstrate and validate state-of-the-art spacecraft autonomy hardware and software in an operational space environment. The Honeywell 1750A GVSC Flight Computer (GFC), developed for the Air Force's Phillips Lab, achieved its primary goal: develop a low-cost, low-risk computer for onboard data processing while demonstrating a secondary goal of transitioning new technologies to flight in a short period of time. The 1750A CPU utilizes the Honeywell RH-1750 Generic VHSIC Spaceborne Computer (GVSC) chipset. The RH-1750 was developed by Honeywell under an Air Force contract and is manufactured using Honeywell's Radiation Insensitive CMOS (RICMOS)TM III process. The GFC is ideally suited for the small satellite environment. Its low cost, low weight, low power, high performance and flexibility make it an excellent candidate for control and data processing applications. The 32- bit GVSC local bus supports zero wait state access to the static RAM resulting in a maximum throughput of 2.5 MIPS under worst-case conditions. The local expansion bus (also 32 bits), accepts up to four I/O assemblies, including DMA capability, and supports I/O throughput rates up to 2 Mwords per second.

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Publication Details

Journal
Digital Commons - USU (Utah State University)
Published
2025-09-09
DOI
https://doi.org/10.26077/5z81-cd07
Citations
1
Primary Topic
Spacecraft Design and Technology
Type
article
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article

Development of a Space Computer - A Low Risk Approach to Control and Data Processing Applications in Small Satellites

Vincent Poole
1 citations
Digital Commons - USU (Utah State University)
Spacecraft Design and Technology
article

Development of a Space Computer - A Low Risk Approach to Control and Data Processing Applications in Small Satellites

Vincent Poole
article en
1 citations

Abstract

In early 1991, Honeywell delivered three RH-1 750A based flight computers to complete the AST III program in support of a Phillips Laboratory Autonomous Navigation Demonstration Satellite. The delivery was significant for the following reasons: it was the first delivery of a space qualified RH-1750A computer, the RH-1750 Multi-Chip Module (MCM) was transitioned from a research and development effort to a B-level flight part, and, design to delivery of the first flight unit was accomplished in only 16 months. The AST III program consists of several sequential efforts which will demonstrate and validate state-of-the-art spacecraft autonomy hardware and software in an operational space environment. The Honeywell 1750A GVSC Flight Computer (GFC), developed for the Air Force's Phillips Lab, achieved its primary goal: develop a low-cost, low-risk computer for onboard data processing while demonstrating a secondary goal of transitioning new technologies to flight in a short period of time. The 1750A CPU utilizes the Honeywell RH-1750 Generic VHSIC Spaceborne Computer (GVSC) chipset. The RH-1750 was developed by Honeywell under an Air Force contract and is manufactured using Honeywell's Radiation Insensitive CMOS (RICMOS)TM III process. The GFC is ideally suited for the small satellite environment. Its low cost, low weight, low power, high performance and flexibility make it an excellent candidate for control and data processing applications. The 32- bit GVSC local bus supports zero wait state access to the static RAM resulting in a maximum throughput of 2.5 MIPS under worst-case conditions. The local expansion bus (also 32 bits), accepts up to four I/O assemblies, including DMA capability, and supports I/O throughput rates up to 2 Mwords per second.

Digital Commons - USU (Utah State University)
Honeywell (United States) (US)
Spacecraft Design and Technology
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Development of a Space Computer - A Low Risk Approach to Control and Data Processing Applications in Small Satellites — Vincent Poole · Digital Commons - USU (Utah State University) (2025) | TGRS Research Map | TGRS