Analysis of gate oxide instability of SiC MOSFETs under ultra-high gate voltage pulse stress

In power electronics, silicon carbide (SiC) MOSFETs can experience ultra-high gate voltage pulses during electrostatic events, yet their reliability under such extreme conditions remains insufficiently explored. In this work, we fabricate SiC MOSFETs and present systematic reliability evaluation under ultra-high gate pulse stress. Our results reveal that hole-related charge trapping dominates the degradation for both positive and negative gate stress. Under high positive pulses, the threshold voltage (<i>V</i>_th) exhibits a non-monotonic shift driven by hole injection, whereas under high negative pulses,<i>V</i>_thdecreases rapidly due to hole capture and the formation of additional donor-like traps. Moreover, the time and field dependence of<i>V</i>_thdegradation demonstrates that oxide breakdown is primarily caused by electric field stress. Overall, this study provides new insight into the degradation pathways of SiC MOSFETs under extreme electrical stress and offers practical guidance for improving device robustness in power applications.