Reviews of the Static, Adoptive, and Dynamic Sampling in Wafer Manufacturing

Semiconductor wafer manufacturing is one of the most complex and data-intensive processes in the industry, encompassing the front-end (FEOL), middle-end (MOL), and back-end (BEOL) stages, involving thousands of interdependent processes. Each stage can introduce potential variability, thereby reducing yield, making metrology and inspection crucial for process control. However, due to capacity, cost, and destructive testing constraints, exhaustive metrology for every wafer or die is impractical. Therefore, this study aims to introduce sampling strategies that have evolved to balance the accuracy, risk, and efficiency of measurement allocation. This review presents a literature review of static, adaptive, and dynamic sampling and discusses recent intelligent sampling techniques. The results show that traditional static sampling provides fixed, rule-based inspection schemes that ensure comparability and compliance but lack responsiveness to process variations. Adaptive sampling introduces flexibility, allowing measurement density to be adjusted based on detected drift, anomalies, or statistical control limits. Building on this, dynamic sampling represents a paradigm shift towards predictive, real-time decision-making driven by machine learning, risk analysis, and digital twin integration. The dynamic framework continuously assesses process uncertainties and prioritizes metrology to maximize information gain, thereby significantly reducing metrology workload without impacting yield or quality. Static, adaptive, and dynamic sampling together constitute a continuous evolution from deterministic control to self-optimizing intelligence. As semiconductor nodes move towards sub-3 nm, this intelligent sampling technology is crucial for maintaining yield, cost competitiveness, and process flexibility in autonomous, data-centric wafer fabs.