Low-voltage-driven memristor framework for efficient neuromorphic computation with STDP functionality

In this work, a low-voltage-driven theoretical memristor framework is presented with its in-depth parametric evaluation and its neuromorphic computing functionalities, including spike-time dependent plasticity (STDP) via Hebbian learning rules. The presented memristor model efficiently emulates the fundamental pinched hysteresis loop under the application of an input voltage amplitude of 10 mV, which enables its adaptability in low-voltage operation. Moreover, the memristor model efficiently emulates its response under the variations in the applied voltage, initial state variable, boundedness of state variable, control parameter for the rate of change of state variable, experimental fitting parameters, magnitude of exponentials, and conductivity slope parameters. These aforementioned parameters significantly affect the response of the memristor model, which further requires their optimization to understand their impact on the memristor characteristics. Therefore, these parameters are scrutinized based on their strong to weak impact on the memristor model response and its suitability in the neuromorphic computation. Additionally, the presented memristor model efficiently emulates various neuromorphic computing characteristics, including potentiation, depression, conductance tuneability, short-term memory (STM), long-term memory (LTM), transition from STM-to-LTM and vice versa , paired pulse facilitation (PPF), synaptic re-stimulation process, and STDP via Hebbian learning rules. Therefore, the presented theoretical memristor framework can be further useful in the in-memory computation circuit hardware, low-voltage logic operation, pattern recognition, and neuromorphic computing.