Power control in semiconductor chips: integration of reinforcement learning and dynamic modelling

As semiconductor technology enters the nanoscale era, power control has become a major challenge impeding chip performance. Traditional heuristic methods fail to handle complex dynamic workloads, while pure reinforcement learning lacks stability and safety. This paper proposes a hybrid intelligent control framework integrating reinforcement learning with dynamic physical modelling. Offline-trained power and performance models offer prior guidance and safety constraints for online decisions. Experiments using Google production cluster data show the framework achieves an average power of 101.3 W - 21.3% lower than on-demand strategies - and a tail latency of 34.1 ms with only 1.2% violation rate. The energy efficiency reaches 15.6 instructions per joule, outperforming existing methods. This study provides an effective solution for energy-aware chip-level power management and introduces new ideas for intelligent cyber-physical systems.

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Publication Details

Journal
International Journal of Information and Communication Technology
Published
2025-01-01
DOI
https://doi.org/10.1504/ijict.2025.150604
Primary Topic
Low-power high-performance VLSI design
Type
article
Field-Weighted Citation Impact
0.00

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article

Power control in semiconductor chips: integration of reinforcement learning and dynamic modelling

Zhanhan Hu
International Journal of Information and Communication Technology
Low-power high-performance VLSI design
article

Power control in semiconductor chips: integration of reinforcement learning and dynamic modelling

Zhanhan Hu
article en

Abstract

As semiconductor technology enters the nanoscale era, power control has become a major challenge impeding chip performance. Traditional heuristic methods fail to handle complex dynamic workloads, while pure reinforcement learning lacks stability and safety. This paper proposes a hybrid intelligent control framework integrating reinforcement learning with dynamic physical modelling. Offline-trained power and performance models offer prior guidance and safety constraints for online decisions. Experiments using Google production cluster data show the framework achieves an average power of 101.3 W - 21.3% lower than on-demand strategies - and a tail latency of 34.1 ms with only 1.2% violation rate. The energy efficiency reaches 15.6 instructions per joule, outperforming existing methods. This study provides an effective solution for energy-aware chip-level power management and introduces new ideas for intelligent cyber-physical systems.

International Journal of Information and Communication TechnologyVol. 26(46)
North China Institute of Aerospace Engineering (CN)
Department of Education of Hebei Province
Openalex Percentile: Top 59%
Low-power high-performance VLSI design
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