CMOS LIF Spiking Neuron Designed with a Memristor Emulator Based on Optimized Operational Transconductance Amplifiers

The proposed work introduces a sizing algorithm to achieve a desired linear transconductance in the optimization of operational transconductance amplifiers (OTAs) by applying the gm/ID method to find the initial width (W) and length (L) sizes of the transistors. These size values are used to run the non-dominated sorting genetic algorithm (NSGA-II) to perform a multi-objective optimization of three OTA topologies. The gm/ID method begins with transistor characterization using MATLAB R2024a generated look-up tables (LUTs), which map normalized transconductance of the transistor channel dimensions, and key performance metrics of a complementary metal–oxide–semiconductor (CMOS) technology. The LUTs guide the initial population generation within NSGA-II during the optimization of OTAs to achieve not only a desired transconductance but also accuracy alongside linearity, high DC gain, low power consumption, and stability. The feasible W/L size solutions provided by NSGA-II are used to enhance the CMOS design of a memristor emulator, where the OTA with the desired transconductance is adapted to tune the behavior of the memristor, demonstrating improved pinched hysteresis loop characteristics. In addition, process, voltage and temperature (PVT) variations are performed by using TSMC 180 nm CMOS technology. The memristor-based on optimized OTAs is used to design a Leaky Integrate-and-Fire (LIF) neuron, which produces identical spike counts (seven spikes) under the same input conditions, though the time period varied with a CMOS inverter scaling. It is shown that increasing transistor widths by 100 in the inverter stage, the spike quantity is altered while changing the spiking period. This highlights the role of device sizing in modulating LIF neuron dynamics, and in addition, these findings provide valuable insights for energy-efficient neuromorphic hardware design.