Degradation comparative study of SIC MOSFETs with different gate structures under dynamic gate stress

This research systematically investigates, for the first time, the varying behavior under dynamic gate stress in silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with different gate architectures. The key findings show that devices with distinct gate structures exhibit notable differences in both the operational range under dynamic gate stress, measured by critical bipolar gate voltage thresholds, and their sensitivity to negative gate bias. The mechanistic analysis attributes these differences to process-dependent interfacial defects and SiC crystallographic anisotropy. The insights gained from this study offer practical design recommendations for optimizing gate structure design, thereby enhancing the dynamic gate stress reliability of high-power SiC devices.